High-Bandwidth Memory Interface Design

  • Share

Instructor: Chulwoo Kim

Chulwoo Kim received the B.S. and M.S. degrees in electronics engineering from the Korea University in 1994 and 1996, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign in 2001. In May 2001, he joined IBM Microelectronics Division, Austin, TX, where he was involved in Cell processor design. Since September 2002, he has been with the Department of Electrical Engineering, Korea University, where he is currently a Professor. In 2008-2009, he was a Visiting Scholar at the University of California, Los Angeles. His current research interests are in the areas of wireline transceiver, memory, power management and data converters. He is currently on the editorial board of the IEEE Transactions on VLSI Systems. 

Memory bandwidth has been increased significantly. There are many technical issues to enhance the memory interface such as TSV interface, high-speed serial interface including equalization, ODT, pre-emphasis, wide I/O interface including crosstalk, skew cancellation, and clock generation and distribution. This tutorial provides overviews of recent advances in memory interface design both in architecture and circuit levels. Subtopics will include signal integrity and testing. The future trends for further bandwidth enhancement will be covered as well.