Yiran Chen


Associate Professor in the Department of Electrical and Computer Engineering

Dr. Yiran Chen received B.S. and M.S. degrees (both with honor) from Tsinghua University, and a Ph.D. from Purdue University in 2005.

After five years in industry, he joined the University of Pittsburgh in 2010 as an assistant professor. He was promoted to associate professor in 2014.

Before coming to Duke in January 2017, he was Bicentennial Alumni Faculty Fellow and co-director of the Evolutionary Intelligence Lab (www.ei-lab.org) in the Pitt Electrical and Computer Engineering Department, focusing on the research of nonvolatile memory and storage systems, neuromorphic computing, and mobile applications.

Dr. Chen has published a book, a dozen of book chapters, and more than 270 journal and conference papers. He has been granted 90 United States and international patents, with other 13 pending applications.

He is the associate editor of IEEE TCAD, IEEE D&T, IEEE ESL, ACM JETC, and ACM SIGDA E-newsletter, and served on the technical and organization committees of around 40 international conferences. He received three best paper awards from ISQED’08, ISLPED’10 and GLSVLS’13, and other 13 nominations from DAC, ICCAD, DATE, ASPDAC, ISLPED, CODES ISSS, and ISQED.

He also received the NSF CAREER award in 2013, and the ACM SIGDA outstanding new faculty award in 2014. He was an invitee to the 2013 U.S. Frontiers of Engineering Symposium of the National Academy of Engineering.


  • Chai, X; Zheng, X; Gan, Z; Han, D; Chen, Y, An image encryption algorithm based on chaotic system and compressive sensing, Signal Processing, vol 148 (2018), pp. 124-144 [10.1016/j.sigpro.2018.02.007] [abs].
  • Wang, D; Ma, L; Zhang, M; An, J; Li, HH; Chen, Y, Shift-Optimized Energy-Efficient Racetrack-Based Main Memory, Journal of Circuits, Systems & Computers, vol 27 no. 05 (2018), pp. 1850081-1850081 [10.1142/S0218126618500810] [abs].
  • Bayram, I; Chen, Y, NV-TCAM: Alternative designs with NVM devices, Integration, the VLSI Journal (2018) [10.1016/j.vlsi.2018.02.003] [abs].
  • Liu, Z; Mao, M; Liu, T; Wang, X; Wen, W; Chen, Y; Li, H; Wang, D; Pei, Y; Ge, N, TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2017) [10.1109/TCAD.2017.2783860] [abs].
  • Yan, B; Yang, J; Wu, Q; Chen, Y; Li, H, A closed-loop design to enhance weight stability of memristor based neural network chips, IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, vol 2017-November (2017), pp. 541-548 [10.1109/ICCAD.2017.8203824] [abs].